//------------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited.
//
//            (C) COPYRIGHT 2008-2013 ARM Limited.
//                ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited.
//------------------------------------------------------------------------------
// Version and Release Control Information:
//
// File Revision       : 149903
// File Date           :  2013-05-08 18:23:05 +0100 (Wed, 08 May 2013)
// Release Information : PL401-r0p1-00eac0
//------------------------------------------------------------------------------
// Purpose : HDL design file for AMBA interface block master domain
//------------------------------------------------------------------------------

//------------------------------------------------------------------------------
//
//                        nic400_ib_chiplink_slv_axi4_tpv_ib_master_domain_ysyx_rv32.v
//
//------------------------------------------------------------------------------
//
//  Overview
// ==========
//
//  Master domain of AMBA Interface Block (IB) 'chiplink_slv_axi4_tpv_ib'.
//
//  This IB is a component of AMIB named chiplink_slv_axi4_tpv
// 
//  32bit to 64bit upsizer
//
//           SIF prot axi4
//           MIF prot axi4
//           SIF DW   32
//           MIF DW   64
//
//           MIF  axi4_m
//           RIF  axi4_m
//           IIF  axi4_m
//           BIF  axi4_m
//
//           ID Width    = 4
//           drive_id    = false
//
//           Burstbrk    = false
//
//------------------------------------------------------------------------------


`include "nic400_ib_chiplink_slv_axi4_tpv_ib_defs_ysyx_rv32.v"

`include "Axi.v"

module nic400_ib_chiplink_slv_axi4_tpv_ib_master_domain_ysyx_rv32
  (
  
    //axi4_m AXI bus

    //AW Channel
    awid_axi4_m,
    awaddr_axi4_m,
    awlen_axi4_m,
    awsize_axi4_m,
    awburst_axi4_m,
    awlock_axi4_m,
    awcache_axi4_m,
    awprot_axi4_m,
    awvalid_axi4_m,
    awregion_axi4_m,
    awready_axi4_m,

    //W Channel
    wdata_axi4_m,
    wstrb_axi4_m,
    wlast_axi4_m,
    wvalid_axi4_m,
    wready_axi4_m,

    //B Channel
    bid_axi4_m,
    bresp_axi4_m,
    bvalid_axi4_m,
    bready_axi4_m,

    //AR Channel
    arid_axi4_m,
    araddr_axi4_m,
    arlen_axi4_m,
    arsize_axi4_m,
    arburst_axi4_m,
    arlock_axi4_m,
    arcache_axi4_m,
    arprot_axi4_m,
    arvalid_axi4_m,
    arregion_axi4_m,
    arready_axi4_m,

    //R Channel
    rid_axi4_m,
    rdata_axi4_m,
    rresp_axi4_m,
    rlast_axi4_m,
    rvalid_axi4_m,
    rready_axi4_m,

    //Inter-domain IB bus

    //AW Inter-domain bus
    aw_data_async,
    aw_rpntr_gry_async,
    aw_rpntr_bin,
    aw_wpntr_gry_async,

    //B Inter-domain bus
    b_data_async,
    b_rpntr_gry_async,
    b_rpntr_bin,
    b_wpntr_gry_async,

    //AR Inter-domain bus
    ar_data_async,
    ar_rpntr_gry_async,
    ar_rpntr_bin,
    ar_wpntr_gry_async,

    //R Inter-domain bus
    r_data_async,
    r_rpntr_gry_async,
    r_rpntr_bin,
    r_wpntr_gry_async,

    //W Inter-domain bus
    w_data_async,
    w_rpntr_gry_async,
    w_rpntr_bin,
    w_wpntr_gry_async,

    //Clock and reset signals
    aclk_m,
    aresetn_m

  );




  // ---------------------------------------------------------------------------
  //  Port definitions
  // ---------------------------------------------------------------------------
  
  //axi4_m AXI bus


  //AW Channel
  output  [3:0]       awid_axi4_m;             //write id of axi4_m AXI bus AW channel
  output  [31:0]      awaddr_axi4_m;           //write address of axi4_m AXI bus AW channel
  output  [7:0]       awlen_axi4_m;            //write length field of axi4_m AXI bus AW channel
  output  [2:0]       awsize_axi4_m;           //write size of axi4_m AXI bus AW channel
  output  [1:0]       awburst_axi4_m;          //write burst length of axi4_m AXI bus AW channel
  output              awlock_axi4_m;           //write lock of axi4_m AXI bus AW channel
  output  [3:0]       awcache_axi4_m;          //write cache field of axi4_m AXI bus AW channel
  output  [2:0]       awprot_axi4_m;           //write prot field of axi4_m AXI bus AW channel
  output              awvalid_axi4_m;          //write valid of axi4_m AXI bus AW channel
  output  [3:0]       awregion_axi4_m;         //write region selection signal
  input               awready_axi4_m;          //write ready of axi4_m AXI bus AW channel

  //W Channel
  output  [63:0]      wdata_axi4_m;            //write data of axi4_m AXI bus W Channel
  output  [7:0]       wstrb_axi4_m;            //write strobes of axi4_m AXI bus W Channel
  output              wlast_axi4_m;            //write last of axi4_m AXI bus W Channel
  output              wvalid_axi4_m;           //write valid of axi4_m AXI bus W Channel
  input               wready_axi4_m;           //write ready of axi4_m AXI bus W Channel

  //B Channel
  input   [3:0]       bid_axi4_m;              //b response id of axi4_m AXI bus B Channel
  input   [1:0]       bresp_axi4_m;            //b response status of axi4_m AXI bus B Channel
  input               bvalid_axi4_m;           //b response valid of axi4_m AXI bus B Channel
  output              bready_axi4_m;           //b response ready of axi4_m AXI bus B Channel

  //AR Channel
  output  [3:0]       arid_axi4_m;             //read id of axi4_m AXI bus AR Channel
  output  [31:0]      araddr_axi4_m;           //read address of axi4_m AXI bus AR Channel
  output  [7:0]       arlen_axi4_m;            //read length of axi4_m AXI bus AR Channel
  output  [2:0]       arsize_axi4_m;           //read size of axi4_m AXI bus AR Channel
  output  [1:0]       arburst_axi4_m;          //read burst length of axi4_m AXI bus AR Channel
  output              arlock_axi4_m;           //read lock of axi4_m AXI bus AR Channel
  output  [3:0]       arcache_axi4_m;          //read cache field of axi4_m AXI bus AR Channel
  output  [2:0]       arprot_axi4_m;           //read prot field of axi4_m AXI bus AR Channel
  output              arvalid_axi4_m;          //read valid of axi4_m AXI bus AR Channel
  output  [3:0]       arregion_axi4_m;         //read region selection signal
  input               arready_axi4_m;          //read ready of axi4_m AXI bus AR Channel

  //R Channel
  input   [3:0]       rid_axi4_m;              //read id of axi4_m AXI bus R Channel
  input   [63:0]      rdata_axi4_m;            //read data of axi4_m AXI bus R Channel
  input   [1:0]       rresp_axi4_m;            //read response status of axi4_m AXI bus R Channel
  input               rlast_axi4_m;            //read last of axi4_m AXI bus R Channel
  input               rvalid_axi4_m;           //read valid of axi4_m AXI bus R Channel
  output              rready_axi4_m;           //read ready of axi4_m AXI bus R Channel

  //Inter-domain IB bus


  //AW Inter-domain bus
  input   [60:0]      aw_data_async;           //AW Channel Data
  output  [1:0]       aw_rpntr_gry_async;      //AW Channel Read Pointer (GRY)
  output              aw_rpntr_bin;            //AW Channel Read Pointer (BIN) for data mux
  input   [1:0]       aw_wpntr_gry_async;      //AW Channel Read Pointer (GRY)

  //B Inter-domain bus
  output  [5:0]       b_data_async;            //B Channel Data
  input   [1:0]       b_rpntr_gry_async;       //B Channel Read Pointer (GRY)
  input               b_rpntr_bin;             //B Channel Read Pointer (BIN) for data mux
  output  [1:0]       b_wpntr_gry_async;       //B Channel Read Pointer (GRY)

  //AR Inter-domain bus
  input   [60:0]      ar_data_async;           //AR Channel Data
  output  [1:0]       ar_rpntr_gry_async;      //AR Channel Read Pointer (GRY)
  output              ar_rpntr_bin;            //AR Channel Read Pointer (BIN) for data mux
  input   [1:0]       ar_wpntr_gry_async;      //AR Channel Read Pointer (GRY)

  //R Inter-domain bus
  output  [70:0]      r_data_async;            //R Channel Data
  input   [1:0]       r_rpntr_gry_async;       //R Channel Read Pointer (GRY)
  input               r_rpntr_bin;             //R Channel Read Pointer (BIN) for data mux
  output  [1:0]       r_wpntr_gry_async;       //R Channel Read Pointer (GRY)

  //W Inter-domain bus
  input   [72:0]      w_data_async;            //W Channel Data
  output  [1:0]       w_rpntr_gry_async;       //W Channel Read Pointer (GRY)
  output              w_rpntr_bin;             //W Channel Read Pointer (BIN) for data mux
  input   [1:0]       w_wpntr_gry_async;       //W Channel Read Pointer (GRY)

  //Clock and reset signals
  input               aclk_m;            
  input               aresetn_m;         


  // ---------------------------------------------------------------------------
  // Internal signals
  // ---------------------------------------------------------------------------

  wire                awvalid_master;
  wire                awready_master;
  wire                arvalid_master;
  wire                arready_master;
  wire                bvalid_master;
  wire                bready_master;
  wire                rvalid_master;



  wire                wr_cnt_empty;
  wire                mask_w;
  wire                mask_r;

  // AW Channel wires at boundary
  // PLoad width 61
  
  wire                aw_boundary_dst_valid;
  wire                aw_boundary_dst_ready;

  wire [60:0]         aw_boundary_dst_data;     // concatenation of the registered inputs


  // AR Channel wires at boundary
  // PLoad width 61
  
  wire                ar_boundary_dst_valid;
  wire                ar_boundary_dst_ready;

  wire [60:0]         ar_boundary_dst_data;     // concatenation of the registered inputs


  // R Channel wires at boundary
  // PLoad width 71
  
  wire                r_boundary_src_valid;
  wire                r_boundary_src_ready;

  wire [70:0]         r_boundary_src_data;     // concatenation of the inputs
  wire [70:0]         r_boundary_dst_data;     // concatenation of the registered inputs


  // W Channel wires at boundary
  // PLoad width 73
  
  wire                w_boundary_dst_valid;
  wire                w_boundary_dst_ready;

  wire [72:0]         w_boundary_dst_data;     // concatenation of the registered inputs


  // B Channel wires at boundary
  // PLoad width 6
  
  wire                b_boundary_src_valid;
  wire                b_boundary_src_ready;

  wire [5:0]          b_boundary_src_data;     // concatenation of the inputs
  wire [5:0]          b_boundary_dst_data;     // concatenation of the registered inputs


  wire [1:0]          aw_rpntr_gry_async;          // gray encoded rd-pointer for aw channel
  wire                aw_rpntr_bin;          // binary encoded pointer for read data mux
  wire [1:0]          aw_wpntr_gry_async;          // gray encoded wr-pointer for full/empty calc

  wire [1:0]          ar_rpntr_gry_async;          // gray encoded rd-pointer for ar channel
  wire                ar_rpntr_bin;          // binary encoded pointer for read data mux
  wire [1:0]          ar_wpntr_gry_async;          // gray encoded wr-pointer for full/empty calc

  wire [1:0]          w_rpntr_gry_async;           // gray encoded rd-pointer for w channel
  wire                w_rpntr_bin;           // binary encoded pointer for read data mux
  wire [1:0]          w_wpntr_gry_async;           // gray encoded wr-pointer for full/empty calc

  wire [1:0]          b_rpntr_gry_async;           // gray encoded rd-pointer for b channel
  wire                b_rpntr_bin;           // binary encoded pointer for read data mux
  wire [1:0]          b_wpntr_gry_async;           // gray encoded wr-pointer for full/empty calc

  wire [1:0]          r_rpntr_gry_async;           // gray encoded rd-pointer for r channel
  wire                r_rpntr_bin;           // binary encoded pointer for read data mux
  wire [1:0]          r_wpntr_gry_async;           // gray encoded wr-pointer for full/empty calc


  // ---------------------------------------------------------------------------
  //  start of code
  // ---------------------------------------------------------------------------




  // ---------------------------------------------------------------------------
  // AW Channel timing block wiring at boundary
  // ---------------------------------------------------------------------------

  // expand the concatenated registered values to the boundary outputs
  assign {
          awid_axi4_m,
          awaddr_axi4_m[31:0],
          awlen_axi4_m,
          awsize_axi4_m,
          awburst_axi4_m,
          awlock_axi4_m,
          awcache_axi4_m,
          awregion_axi4_m,
          awprot_axi4_m} = aw_boundary_dst_data;

  

  assign awvalid_master = aw_boundary_dst_valid;
  assign aw_boundary_dst_ready = awready_master;






  // ---------------------------------------------------------------------------
  // AR Channel timing block wiring at boundary
  // ---------------------------------------------------------------------------

  // expand the concatenated registered values to the boundary outputs
  assign {
          arid_axi4_m,
          araddr_axi4_m[31:0],
          arlen_axi4_m,
          arsize_axi4_m,
          arburst_axi4_m,
          arlock_axi4_m,
          arcache_axi4_m,
          arregion_axi4_m,
          arprot_axi4_m} = ar_boundary_dst_data;

  

  assign arvalid_master = ar_boundary_dst_valid;
  assign ar_boundary_dst_ready = arready_master;






  // ---------------------------------------------------------------------------
  // W Channel timing block wiring at boundary
  // ---------------------------------------------------------------------------

  // expand the concatenated registered values to the boundary outputs
  assign {
          wdata_axi4_m,
          wstrb_axi4_m,
          wlast_axi4_m} = w_boundary_dst_data;

  

  assign wvalid_axi4_m = w_boundary_dst_valid;
  assign w_boundary_dst_ready = wready_axi4_m;




  // ---------------------------------------------------------------------------
  // R Channel timing block wiring at boundary
  // ---------------------------------------------------------------------------

  // the inputs are concatenated to interface to the generic register set
  assign r_boundary_src_data = {
          rid_axi4_m,
          rdata_axi4_m,
          rresp_axi4_m,
          rlast_axi4_m};

  assign r_boundary_src_valid = rvalid_axi4_m;
  assign rready_axi4_m = r_boundary_src_ready;

  assign r_data_async = r_boundary_dst_data;
  

  // ---------------------------------------------------------------------------
  // B Channel timing block wiring at boundary
  // ---------------------------------------------------------------------------

  // the inputs are concatenated to interface to the generic register set
  assign b_boundary_src_data = {
          bid_axi4_m,
          bresp_axi4_m};

  assign b_boundary_src_valid = bvalid_master;
  assign bready_master = b_boundary_src_ready;

  assign b_data_async = b_boundary_dst_data;
  
  // ---------------------------------------------------------------------------
  // Instantiation of Timing Isolation Blocks
  // ---------------------------------------------------------------------------
  //  AW Channel Timing Isolation Register Block on boundary

  // HNDSHK_MODE = fifo
  // PAYLOAD_WIDTH = 61
  nic400_ib_chiplink_slv_axi4_tpv_ib_aw_fifo_rd_ysyx_rv32
  u_aw_fifo_rd
    (
     // global interconnect inputs
     .rresetn               (aresetn_m),
     .rclk                  (aclk_m),
     // inputs
     .src_data              (aw_data_async),
     .dst_ready             (aw_boundary_dst_ready),
     .wpntr_gry_async       (aw_wpntr_gry_async),

     // outputs
     .dst_data              (aw_boundary_dst_data),
     .dst_valid             (aw_boundary_dst_valid),
     .rpntr_gry_async       (aw_rpntr_gry_async),
     .rpntr_bin             (aw_rpntr_bin)
     );



  //  AR Channel Timing Isolation Register Block on boundary

  // HNDSHK_MODE = fifo
  // PAYLOAD_WIDTH = 61
  nic400_ib_chiplink_slv_axi4_tpv_ib_ar_fifo_rd_ysyx_rv32
  u_ar_fifo_rd
    (
     // global interconnect inputs
     .rresetn               (aresetn_m),
     .rclk                  (aclk_m),
     // inputs
     .src_data              (ar_data_async),
     .dst_ready             (ar_boundary_dst_ready),
     .wpntr_gry_async       (ar_wpntr_gry_async),

     // outputs
     .dst_data              (ar_boundary_dst_data),
     .dst_valid             (ar_boundary_dst_valid),
     .rpntr_gry_async       (ar_rpntr_gry_async),
     .rpntr_bin             (ar_rpntr_bin)
     );



  //  R Channel Timing Isolation Register Block on boundary

  // HNDSHK_MODE = fifo
  // PAYLOAD_WIDTH = 71
  nic400_ib_chiplink_slv_axi4_tpv_ib_r_fifo_wr_ysyx_rv32
  u_r_fifo_wr
    (
     // global interconnect inputs
     .wresetn               (aresetn_m),
     .wclk                  (aclk_m),
     // inputs
     .src_valid             (r_boundary_src_valid),
     .src_data              (r_boundary_src_data),
     .rpntr_gry_async       (r_rpntr_gry_async),
     .rpntr_bin             (r_rpntr_bin),

     // outputs
     .src_ready             (r_boundary_src_ready),
     .dst_data              (r_boundary_dst_data),
     .wpntr_gry_async       (r_wpntr_gry_async)
     );



  //  W Channel Timing Isolation Register Block on boundary

  // HNDSHK_MODE = fifo
  // PAYLOAD_WIDTH = 73
  nic400_ib_chiplink_slv_axi4_tpv_ib_w_fifo_rd_ysyx_rv32
  u_w_fifo_rd
    (
     // global interconnect inputs
     .rresetn               (aresetn_m),
     .rclk                  (aclk_m),
     // inputs
     .src_data              (w_data_async),
     .dst_ready             (w_boundary_dst_ready),
     .wpntr_gry_async       (w_wpntr_gry_async),

     // outputs
     .dst_data              (w_boundary_dst_data),
     .dst_valid             (w_boundary_dst_valid),
     .rpntr_gry_async       (w_rpntr_gry_async),
     .rpntr_bin             (w_rpntr_bin)
     );



  //  B Channel Timing Isolation Register Block on boundary

  // HNDSHK_MODE = fifo
  // PAYLOAD_WIDTH = 6
  nic400_ib_chiplink_slv_axi4_tpv_ib_b_fifo_wr_ysyx_rv32
  u_b_fifo_wr
    (
     // global interconnect inputs
     .wresetn               (aresetn_m),
     .wclk                  (aclk_m),
     // inputs
     .src_valid             (b_boundary_src_valid),
     .src_data              (b_boundary_src_data),
     .rpntr_gry_async       (b_rpntr_gry_async),
     .rpntr_bin             (b_rpntr_bin),

     // outputs
     .src_ready             (b_boundary_src_ready),
     .dst_data              (b_boundary_dst_data),
     .wpntr_gry_async       (b_wpntr_gry_async)
     );




  // ---------------------------------------------------------------------------
  //  Address channel transaction counting
  // ---------------------------------------------------------------------------

nic400_ib_chiplink_slv_axi4_tpv_ib_maskcntl_ysyx_rv32 u_maskcntl (
        // Master Interface address channel handshake signals
        .awvalid_m    (awvalid_master),
        .arvalid_m    (arvalid_master),
        .awready_m    (awready_master),
        .arready_m    (arready_master),
        // Master Interface return channel handshake signals
        .bvalid_m     (bvalid_master),
        .bready_m     (bready_master),
        .rvalid_m     (rvalid_master),
        .rready_m     (rready_axi4_m),
        // Mask signals
        .wr_cnt_empty (wr_cnt_empty),
        .mask_w       (mask_w),
        .mask_r       (mask_r),
        // Miscelaneous connections
        .aclk         (aclk_m),
        .aresetn      (aresetn_m)
        );


  
  assign awvalid_axi4_m = (awvalid_master & !mask_w);
  assign arvalid_axi4_m = (arvalid_master & !mask_r);

  assign awready_master = (awready_axi4_m & !mask_w);
  assign arready_master = (arready_axi4_m & !mask_r);

  assign bvalid_master = (bvalid_axi4_m & !wr_cnt_empty);
  assign bready_axi4_m = (bready_master & !wr_cnt_empty);



  assign rvalid_master = rvalid_axi4_m & rlast_axi4_m;

  

  // ---------------------------------------------------------------------------







endmodule
`include "nic400_ib_chiplink_slv_axi4_tpv_ib_undefs_ysyx_rv32.v"
`include "Axi_undefs.v"



// --================================= End ===================================--
